TSMC, the backbone of high technology, announced that the development of 1.4nm class production technology continues at the Future of Logic panel held during the EEE International Electron Devices Meeting (IEDM). TSMC also re-emphasized that mass production will be completed by 2025 using the 2nm class production process.
Target at TSMC is 1.4nm
According to a slide published by SemiAnalysis’ Dylan Patel, TSMC’s 1.4nm production node is officially called A14. For now, TSMC has not announced when it plans to start high-volume production (HVM) on the A14 or the specifics of this process. However, since N2, that is, 2nm, is planned to be made in late 2025 and N2P in late 2026, it would not be wrong to predict that A14 technology will come after these two (2027 – 2028).
When it comes to the specifics of the process, TSMC is unlikely to adopt vertically stacked field effect transistors (CFET) in the A14 technology. So the A14 will likely use the company’s 2nd or 3rd generation gate-all-around (GAAFET) transistors, just like the N2 nodes. Nodes like N2 and A14 require concerted optimization at the system level to truly differentiate and enable new levels of performance, power and features.
It is not yet clear whether TSMC will adopt High-NA EUV lithography tools for A14 process technology in the 2027 – 2028 time frame. Considering that by then Intel (and likely other chipmakers) will have adopted and perfected next-generation EUV lithography machines with 0.55 numerical aperture, it wouldn’t be difficult for TSMC to use them. More will change between now and the arrival of 1.4nm microprocessors, as Intel, Samsung and others develop new technologies for chip manufacturing.
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